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A 0.8 μVRMS 8-channel front-end for EEG recording

Research paper by Guocheng Huang, Tao Yin, Haigang Yang, Xinxia Cai

Indexed on: 13 Feb '19Published on: 12 Feb '19Published in: Analog Integrated Circuits and Signal Processing



Abstract

A CMOS low-power 8-channel electro-encephalograph front-end circuit is presented. The single-stage instrumental amplifier in each channel employs current-reuse and chopper-stabilization technology to improve power and noise performance. An output-current-tuning ripple reduction loop (RRL) is designed to reduce the intrinsic offset of the instrumental amplifier and attenuate the chopping ripple. The proposed circuit is implemented in standard 0.18 μm CMOS process. The measured mid-band gain of the front-end is 72.5/75/78.2/81 dB and the high-pass cut-off frequency is 110/150/160/210 Hz. An input-referred noise of 0.8 μVRMS (< 100 Hz), 114 dB CMRR and 102 dB PSRR are achieved at a power consumption of 7.4 μW per channel. The proposed RRL helps to suppress the chopping ripple to a level sufficiently lower than the indigenous circuit noise.